Semiconductor devices are commonly formed in one surface of a semiconductor wafer, such as a silicon wafer, and, after the fabrication process is complete, the individual die are separated (singlulated) by sawing or the like. It is possible to fabricate both top and bottom surfaces of the wafer to form double sided die which may have MOSgated device diffusions and electrodes on both surfaces with a centrally disposed common drain region common to both devices. Alternatively, other semiconductor patterns such as diodes could be formed in one or both surfaces of the wafer, again with the center of the wafer forming a common region to both devices.
The cost of producing the double sided device die is about 50% higher than the conventional single active surface die, but produces twice as many devices and reduces the “foot print” or mounting area on a circuit board to which the die are to be mounted.
Since the double sided devices using MOSFETs, for example, have epitaxially deposited layers (“epi”) on both die or wafer surfaces which receive the device junctions, it is difficult to make contact to the central common drain, for example, an N+ or P+ substrate which is sandwiched between the top and bottom epi layers.
For low voltage power devices a diffusion from the top surface may be used to access the central drain region. This, however, will reduce the top device source region area and reduce the source area metallization which adversely increases the device on resistance RDSON. For higher voltage power devices, with a thicker epi layer, the diffusion time will be very long. For example, to access the N+ substrate of a 600 volt power FET from the top, it would be necessary to drive a phosphorus doping species 60 microns. Again this would take up a large portion of the source region area, so a large area die would be needed to keep RDSON sufficiently low.